CLKOUTSEL=000, NMIDIS=0, SAR_TRG_CLK_SEL=00
System Control Register
| NMIDIS | NMI Disable 0 (0): NMI enabled 1 (1): NMI disabled |
| PLL_VLP_EN | PLL VLP Enable |
| PTC2_HD_EN | PTC2 HighDrive Enable |
| SAR_TRG_CLK_SEL | SAR ADC Trigger Clk Select 0 (00): Bus Clock (During Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop) 1 (01): ADC asynchronous Clock 2 (10): ERCLK32K 3 (11): OSCCLK |
| CLKOUTSEL | Clock out Select 0 (000): Disabled 1 (001): Gated Core Clk 2 (010): Bus/Flash Clk 3 (011): LPO clock from PMC 4 (100): IRC clock from MCG 5 (101): Muxed 32Khz source (please refer SOPT1[19:18] for possible options) 6 (110): MHz Oscillator external reference clock 7 (111): PLL clock output from MCG |